As semiconductor devices become more integrated and/or increase their storage capacity, there may be an increased risk of memory defects in memory cells of semiconductor devices. A yield of semiconductor devices may be reduced when increasing numbers of semiconductor devices have memory defects. By conventional methods, a semiconductor device with a single memory defect may be determined to be a production failure, thereby lowering the yield of the semiconductor device.
Various methods of improving the yield of semiconductor devices have been proposed. For example, a redundancy technique including a fuse circuit is a conventional method for increasing the yield of semiconductor devices.
Redundancy techniques have been widely used in the conventional art. Redundancy techniques may be employed by replacing a memory cell including a memory defect with a memory cell without the memory defect.
By the conventional art, there may be two methods of employing redundancy techniques.
In the first conventional method, a fuse may be cut with a laser device.
In the second conventional method, an electric current may flow into the fuse so that the fuse may exceed an electric current threshold and burn out. The second conventional method may be referred to as an Electric Fuse (E-Fuse) method.
By the conventional art, the E-Fuse method may only be used after an assembly of a semiconductor chip package has been completed. With the E-Fuse method, it may be possible to replace a memory cell with a memory defect with a memory cell without a defect only after complete assembly of the semiconductor chip package.
FIG. 1 illustrates a conventional fuse circuit 100.
Referring to FIG. 1, the conventional fuse circuit 100 may include a first fuse resistor R1 and a second fuse resistor R2. The fuse resistors R1 and R2 may have different resistances. As shown, a PMOS transistor P1 may include a source and a drain. The source of PMOS transistor P1 may be connected to a terminal of the fuse resistor R1, and the drain of the PMOS transistor P1 may be connected to a node A. A PMOS transistor P2 may include a gate which may be connected to the node A. The PMOS transistor P2 may also include a source and a drain. The source of the PMOS transistor P2 may be connected to the fuse resistor R2, and the drain of the PMOS transistor P2 may be connected to a node B. A gate of the PMOS transistor P1 may be connected to the node B. A NMOS transistor N1 may include a drain which may be connected to the node A. The NMOS transistor N1 may also include a source which may be connected to a ground terminal GND. The NMOS transistor N1 may further include a gate which may be connected to the node B. A NMOS transistor N2 may include a gate, a drain and a source. The gate, the drain, and the source of NMOS transistor N2 may be connected to the node A, the node B and the ground terminal GND, respectively.
However, the above-described E-Fuse method may not be completely accurate, thereby making it be difficult to verify whether the E-Fuse method successfully burns out an appropriate fuse.